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CMOS skill is the most fundamental and talented technology in relations of sizing, speed, active power dissipation, high performance & device & circuit level working, etc. The nonstop scrambling in MOSFET length has focused to several challenges that is disappearing gate control on the channel station that marks in Short Channel Effects (SCEs) and heavy leak current. By minimizing the size of the planar transistor i.e. MOSFET below 22nm, several unsolicited effects are occurring like Punch through, subthreshold slope & leakage current. Due to such heavy SCE over nanometer regime, gate is unable to control the channel in the semiconductor(Anju, 2016). To overcome the SCEs, innovative device designs had expected. Multi-gate MOSFET generally considered as Fin-FET which has exposed better downscaling features and improve the performance in terms of speed & low power consumption when related to the MOSFET constructions, due to better gate controllability over the channel.
Fin-FET innovation has been conceived because of the expansion in the degrees of integration. The overview on novelty upgradation activate from vacuum tubes, Point contact diode, BJT, FET, JFET, MOSFET, DG-MOSFET, TG-MOSFET. The gates wound around the channel from the front, top & back sides in Fin-FETs structure, thus the successful diffusion of carriers toward the gate from all sides. By adding the subsequent & third base gate terminal in the device design, the control action on the channel layer increases quickly which thereby dropping DIBL & SS (Shukla, 2017). Triple gate MOSFET (Single TG Fin-FET) is one of the skilled candidates since it has its non-planar assembly, outstanding roll-off features, improved ION & IOFF current and compatibility with the fabrication techniques of conventional MOSFET. Fin-FET devices are clearly mentioned in the International Telecommunication Roadmap for Semiconductor (ITRS) for having a improved performance for scaling CMOS below 22 nm (Prathima et al 2012). As the gate dielectric gets higher k dielectrics or thinner, channel control by the gate rises that result in decrease in DIBL and SS with thinner gate oxide. Fin-FET provides improved scalability due to its brilliant safety to SCE by progress in drive current and transconductance, lower leakage current compared to bulk MOSFETs.(Mishra, 2011)
The gate dielectric materials should have better-insulating properties. So, in this work, the effect by changing the high-k gate dielectrics & metal work function observe on the device. The Fin-FET device is modelled by fluctuating the low dielectric material with high k dielectrics and observe the effect on the performance of leakage current, DIBL(Chopade & Padole, 2017a; Ranka & Rana, 2011). The leakage current has an essential helping of power consumption. Due to the reduction in size of the device continuously leakage current growths towards the output. The advantage of multi-gate Fin-FET is the lower leakage current, higher on-state current & layout flexibility. Figure 1 represents Construction of Fin-FET.
In this research work novel vertically aligned triple -gate bulk Fin-FET is design in COMSOL Multiphysics at nanoscale. The three gates of a Fin-FET have gate terminal shorted for the observation of lower leakage or compact transistor total. Present Study on Fin-FET design discussing about the remedy to drain leakage current using high-κ gate stack and Fin-FET technology up to 14 nm feature size. Smaller thickness, even being an insulator, the leakage current density increases drastically.(Fan, 2016)
This paper is organized as follow: Section II describes Fin-FET Role in Scaling & its fundamental. In Section III the device structure & geometry parameter details use in design. Section IV we present analysis detailing on how High-K Dielectrics & metal work function reduces leakage current & other performance parameters. Section V shows the obtained results by changing metal work function & gate dielectrics.